The present invention relates to semiconductor devices, and more particularly, to a method of electrically testing a semiconductor memory device.
Semiconductor devices are produced in a wafer state, assembled as semiconductor packages, and electrically tested before being delivered to users. Because semiconductor memory devices have recently become high capacity, high speed, multi-pin devices (such as DRAMs), the efficiency of their electrical test processes must be increased. To increase the efficiency of the electrical test processes, testers focus on higher velocities and improvement of throughput time. Throughput time can be improved in various ways. One way to improve throughput time is by controlling a test program. Another way to increase throughput rate and improve throughput time is to increase the number of semiconductor memory devices that can be tested simultaneously, i.e., by testing an increased number of devices in parallel.
FIG. 1 is a block diagram of a conventional tester 100 for testing a semiconductor memory device 300. A tester 100 can be used to detect defects that occur in a wafer fabricating process or in an assembling process and can thereby screen-out good products. Referring to FIG. 1, a tester 100 may interface with a device under test (DUT) 300 by way of an interface board 200 having a socket for seating the DUT 300. A handler (not shown) may be used to load the DUT 300 into the socket of the interface board 200 (also referred to as a “socket board”).
Tester 100 has a test processor 110 for controlling hardware components within the tester 100. The hardware components may include, for example, a programmable power supply 112, a direct current (DC) parameter measurement unit 114, an algorithmic pattern generator 116, a timing generator 118, a wave shape formatter 120, and pin electronics 150. The pin electronics 150 can include a driver signal channel (not shown), and an input/output (I/O) signal channel (not shown). The pin electronics 150 may also include a comparator. The tester 100 operates test programs of the test processor 110 to cause the hardware components to exchange signals with each other to test electrical functions of the DUT 300 via the pin electronics 150 and the socket board 200.
The test programs can include a DC test program, an alternating current (AC) test program, and a functional test program. The functional test program may ascertain the function of a semiconductor memory device (e.g., a DRAM) during actual operation. In other words, the tester 100 may write an input pattern of the algorithmic pattern generator 116 into the DRAM being tested (DUT 300). The tester may then read the pattern from the DRAM and compare the pattern read with that of an expected pattern using the comparator.
FIG. 2 is a block diagram illustrating certain characteristics of a driver channel and an input/output (I/O) channel. Driver and I/O channels may be disposed in the pin electronics 150 of the tester 100 shown in FIG. 1. Referring to FIG. 2, the maximum number of DUTs 300 that can be tested in parallel in the tester 100 is limited by the number of channels of the pin electronics 150. The channel of pin electronics 150 may comprise a driver signal channel 152 and I/O signal channel 154.
The driver channel 152 may fan-out to drive multiple pins of the DUT 300 in the socket board 200. Fanning out to multiple pins may enable an increase in the number of DUTs 300 that can be driven in parallel within the electrical test process. In this manner, one driver channel 152 can control two or more address pins or control pins of the DUT 300.
The I/O signal channel 154 can read data from the DUT 300. The data may be kept unique to enable pattern comparisons with an expected pattern in tester 100. Thus, unlike the driver signal channel 152, the I/O signal channel 154 cannot share I/O data pins DQ of the DUT 300 in the socket board. In other words, conventionally, an I/O signal channel 154 can only be connected to one data pin DQ of the DUT 300 at a time. The maximum number of DUTs that can be tested in parallel within a conventional tester 100 is therefore related both to the number of I/O signal channels of the pin electronics 150 of the tester 100 and to the number of data pins of the DUT 300. For this reason, the number of I/O signal channels 154 in the pin electronics 150 of the tester 100 and the pin count of the DUT 300 determines the maximum number of DUTs that may be tested in parallel in the tester 100. For example, twice as many eight-pin DUTs as sixteen-pin DUTs can be tested in parallel in the conventional tester 100.
FIG. 3 is a flowchart illustrating a conventional method 305 of testing semiconductor memory devices. Referring to FIGS. 1-3, a socket board 200 is conventionally configured to establish connections for data pins of a DUT 300 in one-to-one relationship with I/O signal channels of the pin electronics 150 of a tester 100 (block 310). An electrical test begins (block 320) after the socket board 200 has been configured to interface and connect the tester 100 to the DUT 300. The tester 100 then reads (block 330) data output from the data pins of the DUT 300 one-at-a-time during functional test operations of the DUT 300 via I/O signal lines of the socket board 200.
This method of operation allows unique data to be read and compared individually with the expected pattern in the tester. For example, sixteen data pins of a DUT can permit testing of two separate eight-bit units. Sixteen data bits may be read together and compared with an expected two-byte pattern in the tester. Thus, increasing the number of data pins DQ of a DUT (e.g., from eight to sixteen data pins) may result in a decrease in device throughput rate in an electrical test process in a conventional tester 100, because of the limiting one-to-one relationship between data pins and respective I/O signal channels.